DS DS/CLC/R 217-004 JESSI 0.8 µm CMOS transistor model for analogue and digital circuit simulation

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DS DS/CLC/R 217-004 Document Information:

Title
JESSI 0.8 µm CMOS transistor model for analogue and digital circuit simulation

JESSI 0.8 µm CMOS-transistormodel for analog og digital kredsløbssimulering

Dansk Standard

Publication Date:
Aug 14, 1997

Scope:

This work has been performed as part of the European Microelectronics program JESSI within project AC41 Technology Assessment. This report describes the complete model equations of the JESSI 0.8 µm CMOS transistor model for analog and digital circuit simulation in the deep submicron region.

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